Low-Density Parity-Check (LDPC) codes with iterative decoding based on belief propagation algorithm (also known as the sum-product (SP) algorithm) have excellent error correcting capability approaching the Shannon limit. Moreover, very high decoding throughput can be achieved since the SP decoding algorithm is inherently fully parallelizable.
Recently, LDPC codes have been adopted as the FEC (forward error correction) coding scheme for many digital communication standards. In particular, the RS (Reed-Solomon)-based LDPC code (see, I. Djurdjevic, J. Xu, K. Abdel-Ghaffar, and S. Lin, “A class of low-density parity-check codes constructed based on Reed-Solomon codes with two information symbols,” IEEE Communications Letters, Vol. 7, pp. 317-319, 2003) has been adopted to be used in 10 Gigabit Ethernet over copper (10GBASE-T). The RS-based LDPC codes are constructed based on an algebraic method. This method is based on the structure of Reed-Solomon codes with two information symbols. Constructed RS-based LDPC codes are free of cycles of length 4 and have good minimum distances. For example, a regular (2048, 1723) RS-based LDPC code whose column and row weights are 6 and 32 has at least 8 minimum distance. At the BER (bit error rate) of 10−6 assuming BPSK (binary phase shift keying) transmission over an AWGN (additive white gaussian noise) channel, the code performs at a distance of 1.55 dB from the Shannon limit and achieves a 6 dB coding gain over the uncoded BPSK.
LDPC codes are identified by parity-check matrices and LDPC code decoder complexity depends on the structure pattern of the parity-check matrix. In other words, if a parity-check matrix has a specific regular pattern, it can be used to design a low complexity decoder architecture. The parity-check matrix of the RS-based LDPC codes is simple in structure since it consists of square matrices. However, if a constraint such that the row weight of parity-check matrix is equal to the size of submatrix is not satisfied, these submatrices do not result in circulant matrices, i.e., each submatrix is not cyclically shifted version of identity matrix. In this case, it may appear that the parity-check matrix doesn't have any kind of regular pattern. Thus this fact makes it hard to derive an efficient memory address generation (MAG) scheme for the time-multiplexed (TM) RS-based LDPC decoder architectures (for the TM LDPC decoder architecture, see, T. Zhang and K. K. Parhi, “Joint (3,k)-regular LDPC code and decoder/encoder design,” IEEE Trans. Acoust., Speech, Signal Processing, Vol. 52, pp. 1065-1079, April 2004) though a simple MAG scheme is essential for any kind of TM LDPC code decoder architecture.
For high decoding throughput applications such as the 10GBASE-T, it may be difficult to implement a RS-based LDPC decoder based on the TM decoder architecture since the number of clock cycles required per each iteration in the architecture is directly proportional to the size of the submatrix. For example, the RS-based LDPC code used in the 10GBASE-T has 64×64 submatrix and 128 (=2*64) clock cycles are required per each iteration. In addition, since a large volume of messages are passed between memories and processing units, the number of required processing units is significantly large. Thus, a methodology for designing new TM RS-based LDPC code decoders oriented for high decoding throughput should be developed, which can leads to a low-cost decoder architecture.
What is needed is a new MAG scheme for the TM RS-based LDPC code decoder and a methodology that leads to low cost decoder architectures allowing high throughput.